Significant challenges are posed when designing precision analog circuits with DMOS (Double-Diffused Metal Oxide Semiconductor) transistors having greater than 100V breakdown voltage. These devices may use thicker gate oxides, which make matching difficult (and mismatches cause problems as discussed herein). In order to achieve high VDS (wherein VDS is the voltage difference between the transistor drain and source) breakdowns and reduce the effects of high electric fields, these devices have predefined layouts that may be circular or orthogonal. As a result, common layout techniques for matching of MOS transistors may not be employed for their high voltage counterparts. The high voltage devices are usually not scalable, and thus optimizing device sizes for better matching is a challenge.
Mismatches among transistors can result in a variety of imperfections in analog circuits. In operational amplifiers, differential amplifiers, and operational transconductance amplifiers, mismatching typically causes input referred offset voltages that drift with temperature. Mismatches between DMOS transistors may cause input offset voltages as high as 25 mV and offset drifts of over 60 uV/° C. Mismatches between output buffer circuits and the previous gain stages in operational amplifiers can cause higher than expected quiescent current. In dual gain cross-coupled differential amplifier stages, two active load mismatches in the current mirrors can cause the bias current in the differential amplifier to drop to zero. In recent years, there has been a growing demand for high voltage analog integrated circuits, particularly in the field of test and measurement. In order to meet the high voltage and precision requirements at the same time, new design techniques are required.
Trimming may be employed to reduce effects such as offset voltage, temperature drift, and excessive quiescent current. FIG. 1 is an illustration of a schematic diagram illustrating trimming techniques for amplifiers as known in the prior art. FIG. 1 shows a standard operational transconductance amplifier 10 with various common trimming options. The operational transconductance amplifier 10 may be used in a front end of an operational amplifier.
FIG. 1 shows three different trim networks applied symmetrically for the operational transconductance amplifier 10. The first trim network 12 adjusts the sizes of the input transistors 14. The second trim network 16 uses one or more source resistors 18 to trim an offset. The third trim network 20 adjusts current source loads for trimming. It should be noted that the trim networks 12, 16, and 20 include elements that are inherent to the operational transconductance amplifier 10. The switches shown in FIG. 1 can be implemented using Zener zaps, poly or metal fuses, CMOS switches, or other similar devices as known to those having ordinary skill in the art.
For a high voltage operational transconductance amplifier 10, each of the aforementioned trim networks 12, 16, 20 is flawed. More specifically, the first trim network 12 uses fractional input transistors 14 for adjusting offset. Since high voltage devices may not be scalable and may occupy substantial die area and increase the input capacitance of the amplifier, the first trim network 12 is not a desirable option. The second trim network 16 uses resistors 18, which typically consume substantial die area. Furthermore, the drop across the resistor 18 reduces a negative swing of the operational transconductance amplifier 10. The third trim network 20 has flaws that are similar to the first trim network 12. Thus, none of the traditional trimming methods for the operational transconductance amplifier 10 are viable options for high voltage amplifier mismatch adjustment. A matching method and apparatus that are scalable and consume limited die area are desirable.
Thus, a need exists in the industry to address the aforementioned deficiencies and inadequacies.